Underfill process and materials for singulated heat spreader stiffener for thin core panel processing

ABSTRACT

A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed.

FIELD

The present invention relates to methods of fabricating microelectronic packages, and especially to an underfill process and materials for singulated heat spreader stiffener for thin core panel processing.

BACKGROUND

As microelectronic components shrink in size, a trend has emerged to provide package substrates that may be characterized as thin core substrates (that is, substrates having a core with a thickness less than or equal to 400 microns and larger than zero), or no-core substrates (that is, substrates without cores).

Disadvantageously, with a thin or no-core substrate, however, errors may occur during the package manufacturing process, such as, for example, during flip chip bonding where substrate flatness and rigidity are required. To address the above issue, the prior art sometimes provides substrates that may have a thickness of at least several tens of microns or more. However, the above measure disadvantageously detracts from further package size minimization.

The prior art fails to provide method or structures that address the above disadvantages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graphical illustration of a bottom of an example integrated heat spreader (“IHS”) panel, in accordance with one example embodiment of the invention;

FIG. 2 is a graphical illustration of a top of an example substrate panel, in accordance with one example embodiment of the invention;

FIGS. 3 is a graphical illustration of a cross-sectional view of an example assembly, in accordance with one example embodiment of the invention;

FIG. 4 is a flowchart of an example method for manufacturing a microelectronic device package, in accordance with one example embodiment of the invention; and

FIG. 5 is a block diagram of an example electronic appliance suitable for implementing a microelectronic device package including an IHS described herein, in accordance with one example embodiment of the invention.

For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.

DETAILED DESCRIPTION

In the following detailed description, a method of making a microelectronic package, and a microelectronic package made according to the method are disclosed. Reference is made to the accompanying drawings within which are shown, by way of illustration, specific embodiments by which the present invention may be practiced. It is to be understood that other embodiments may exist and that other structural changes may be made without departing from the scope and spirit of the present invention.

The terms on, above, below, and adjacent as used herein refer to the position of one element relative to other elements. As such, a first element disposed on, above, or below a second element may be directly in contact with the second element or it may include one or more intervening elements. In addition, a first element disposed next to or adjacent a second element may be directly in contact with the second element or it may include one or more intervening elements.

Referring first to FIG. 1, an example integrated heat spreader (“IHS”) panel 100 includes IHS components 101, panel perimeter ribs 102, die sites 104, component perimeter ribs 106, component perimeter rib gaps 108, die site gates 110, openings 112, and porous plugs 114, as shown in FIG. 1. According to embodiments, IHS panel 100 may include stamped or cast copper, or may include any other material adapted to be used as a heat spreader including the protrusions described hereinafter, as would be within the knowledge of a skilled person. In one embodiment, IHS panel 100 is formed from injection molded magnesium. Integrated circuit dies may be bonded and thermally coupled to die sites 104 of a corresponding one of the IHS components 101 of IHS panel 100 to yield a die-carrying IHS panel. The dies may for example be bonded (that is, mechanically fixed to) and thermally coupled (that is, coupled for enhanced thermal conductivity) to die sites 104 of the respective ones of the IHS components 101 using a thermal interface material (TIM), as would be within the knowledge of the skilled person. While shown as including 24 IHS components 101, IHS panel 100 may include any number of IHS components 101.

IHS panel 100 includes protrusions that extend perpendicularly from a bottom surface of IHS components 101. Panel perimeter ribs 102 protrude perpendicularly from a perimeter of IHS panel 100 and are able to couple and form an air-tight seal with a corresponding substrate panel, for example as shown in FIG. 2. Component perimeter ribs 106 protrude perpendicularly from and define the borders between IHS components 101. Component perimeter rib gaps 108 allow for the flow of underfill material between the spaces formed between IHS components 101 and the corresponding substrate. Die site gates 110 also protrude perpendicularly from IHS components 101 and are situated near die sites 104 so as to channel underfill material under a die as part of a method of manufacturing an integrated circuit device package, for example as described in reference to FIG. 4. The protrusions from IHS panel 100, namely panel perimeter ribs 102, component perimeter ribs 106 and die site gates 110, comprise a height generally coextensive with a height of an IC die bonded with each of IHS components 101.

IHS panel 100 of the shown embodiments defines a plurality of openings 112 extending through a thickness thereof, that is, extending from a die-carrying surface of IHS panel 100 all the way to an opposite, backside surface of IHS panel 100. Openings 112 may be utilized to inject underfill material into a space between IHS panel 100 and a corresponding substrate panel as described hereinafter. IHS panel 100 also defines a plurality of porous plugs 114. Porous plugs 114 comprise any suitable material through which air can, but underfill material can not, pass. While shown as including a same number of openings 112 as porous plugs 114, IHS panel 100 may include any number of openings 112 and porous plugs 114. In one embodiment, the plurality of openings 112 in IHS panel 100 is greater than the plurality of porous plugs 114.

Referring next to FIG. 2, an example substrate panel 200 includes substrate components 201, die interconnects 202, perimeter sealant pattern 204, component sealant pattern 206 and sealant gaps 208, as shown in FIG. 2. According to embodiments, substrate panel 200 may include any type of package substrate within the knowledge of a skilled person, such as, for example, one of a BGA substrate, a LGA substrate and a PGA substrate. According to one embodiment, substrate panel 200 includes at least one of thin substrates and no-core substrates. Substrate panel 200 contains a plurality of substrate components 201 each for bonding with an active surface of an IC die and an IHS component 101. Die interconnects 202 may be any interconnect within the knowledge of a skilled person, such as for example an array of solder balls. A top surface of substrate panel 200 include patterns of sealant for bonding with corresponding protrusions of IHS panel 100. For example, perimeter sealant pattern 204 is disposed around the perimeter of substrate panel 200 for bonding with panel perimeter ribs 102. Component sealant pattern 206 defines boundaries between substrate components 201 and bonds with component perimeter ribs 106. Sealant gaps 208 correspond with component perimeter rib gaps 108.

Referring next to FIG. 3, an example assembly 300 includes IHS panel 100, panel perimeter ribs 102, component perimeter ribs 106, die site gates 110, opening 112, porous plugs 114, substrate panel 200, die interconnects 202, perimeter sealant pattern 204, component sealant pattern 206, IC dies 302, underfill 304 and cut-line 306, as shown in FIG. 3. IC dies 302 may be bonded with IHS panel 100 before panel perimeter ribs 102 and component perimeter ribs 106 of IHS panel 100 are bonded with perimeter sealant pattern 204 and component sealant pattern 206 of substrate panel 200, respectively. The IC dies 302 of die-carrying IHS panel 100 may, according to an embodiment, be flip chip mounted onto die interconnects 202 of substrate panel 200 using a solder reflow process in a well known manner. Underfill 304 may be injected through opening 112 into spaces between IHS panel 100 and substrate panel 200 and forced around die site gates 110 into die interconnects 202 through vacuum suction applied through porous plugs 114. Underfill 304 may comprise any type of underfill polymers including, but not limited to, epoxy, silicone, TPO, PE/PP copolymers, urethane polymers including resin transfer molding (low pressure) and injection transfer molding (high pressure). Cut-line 306 represents where assembly 300 may be cut to singulate a microelectronic package including a package substrate component 201, an IC die 302, and an IHS component 101 being coextensive in its width and its length with respect to the package substrate.

Referring now to FIG. 4, an example method 400 for manufacturing a microelectronic device package begins with bonding (402) a plurality of IC dies 302 to IHS panel 100 to yield a die-carrying IHS panel. In one embodiment, the IC dies 302 are bonded to IHS panel 100 using a thermal interface material. At some point a sealant is dispensed (404) in patterns on a top surface of substrate panel 200. Next, perimeter ribs (for example 102 and 106) of IHS panel 100 are mounted (406) to corresponding sealant patterns (for example 204 and 206) on substrate panel 200 to yield a combination including the die-carrying IHS panel mounted to the substrate panel. IC dies 302 are bonded (408) and solder reflowed with die interconnects 202 of substrate panel 200. Air is evacuated from and underfill is injected into (410) the spaces between IHS panel 100 and substrate panel 200. In one embodiment, a vacuum is created by applying suction to porous plugs 114 thereby evacuating air, but blocking the escape of underfill material. In one embodiment, underfill is forcibly injected through openings 112. Provision of the underfill material may involve curing the same, as would be recognized by the skilled person. Lastly, IC packages are singulated (412) from the assembly 300 for example by a saw cutting along cut-line 306.

FIG. 5 is a block diagram of an example electronic appliance suitable for implementing a microelectronic device package including an IHS described herein, in accordance with one example embodiment of the invention. Electronic appliance 500 is intended to represent any of a wide variety of traditional and non-traditional electronic appliances, laptops, desktops, cell phones, wireless communication subscriber units, wireless communication telephony infrastructure elements, personal digital assistants, set-top boxes, or any electric appliance that would benefit from the teachings of the present invention. In accordance with the illustrated example embodiment, electronic appliance 500 may include one or more of processor(s) 502, memory controller 504, system memory 506, input/output controller 508, network controller 510, and input/output device(s) 512 coupled as shown in FIG. 5. Processor(s) 502, or other integrated circuit components of electronic appliance 500, may comprise a microelectronic device package including an IHS as described previously as an embodiment of the present invention.

Processor(s) 502 may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s) 502 are Intel® compatible processors. Processor(s) 502 may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system.

Memory controller 504 may represent any type of chipset or control logic that interfaces system memory 506 with the other components of electronic appliance 500. In one embodiment, the connection between processor(s) 502 and memory controller 504 may be a point-to-point serial link. In another embodiment, memory controller 504 may be referred to as a north bridge.

System memory 506 may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s) 502. Typically, though the invention is not limited in this respect, system memory 506 will consist of dynamic random access memory (DRAM). In one embodiment, system memory 506 may consist of Rambus DRAM (RDRAM). In another embodiment, system memory 506 may consist of double data rate synchronous DRAM (DDRSDRAM).

Input/output (I/O) controller 508 may represent any type of chipset or control logic that interfaces I/O device(s) 512 with the other components of electronic appliance 500. In one embodiment, I/O controller 508 may be referred to as a south bridge. In another embodiment, I/O controller 508 may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003.

Network controller 510 may represent any type of device that allows electronic appliance 500 to communicate with other electronic appliances or devices. In one embodiment, network controller 510 may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller 510 may be an Ethernet network interface card.

Input/output (I/O) device(s) 512 may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance 500.

In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims. 

1. A method of making a microelectronic package comprising: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel; and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel.
 2. The method of claim 1, further comprising evacuating air from a space between the IHS panel and the substrate panel of the combination through a porous plug extending through a thickness of the IHS panel.
 3. The method of claim 2, further comprising injecting an underfill material into the space between the IHS panel and the substrate panel of the combination through an opening extending through a thickness of the IHS panel.
 4. The method of claim 1, further comprising singulating the combination to yield a plurality of microelectronic packages, each of the packages including: an IHS component of the IHS panel, one of the plurality IC dies bonded and thermally coupled to said IHS component, and one of the plurality of package substrates, said IHS component and said one of the plurality of IC dies being mounted to said one of the plurality of package substrates to form said each of the packages.
 5. The method of claim 1, wherein bonding a plurality of IC dies includes bonding the dies to the IHS panel using a thermal interface material.
 6. The method of claim 1, wherein mounting the die-carrying IHS panel onto the substrate panel includes using a solder reflow process.
 7. The method of claim 1, further comprising: dispensing sealant onto the substrate panel in a pattern corresponding to protruding gates on the IHS near the IC dies; and bonding the gates of the IHS to the sealant on the substrate.
 8. A microelectronic package comprising: a package substrate; an IC die mounted to the substrate; and an IHS bonded and thermally coupled to the die such that the die is between the substrate and the IHS, the IHS being coextensive in its width and in its length with respect to the package substrate, wherein the IHS includes a perimeter rib that extends to and bonds with a top surface of the package substrate.
 9. The package of claim 8, further including an underfill material disposed between the package substrate and the IHS.
 10. The package of claim 8, wherein the IHS comprises injected molded magnesium.
 11. The package of claim 8, wherein the IHS comprises a porous plug.
 12. The package of claim 8, wherein the IHS comprises an opening that extends through a thickness of the IHS.
 13. The package of claim 8, wherein the IHS comprises a protruding gate near the IC die, the gate being coextensive in height with respect to the IC die.
 14. An apparatus comprising: an IHS panel including a plurality of IHS components each containing a site to receive and bond with an IC die, wherein the IHS panel includes perimeter ribs that protrude perpendicularly from the IHS components, wherein the IHS panel includes a porous plug, and wherein the IHS panel includes an opening extending through a thickness of the IHS panel.
 15. The apparatus of claim 14, wherein the IHS panel further comprises gates which protrude perpendicularly from the IHS components near the IC die sites.
 16. The apparatus of claim 14, wherein the IHS panel further comprises a plurality of openings and porous plugs.
 17. The apparatus of claim 16, wherein the plurality of openings is greater than the plurality of porous plugs.
 18. The apparatus of claim 14, further comprising a plurality of IC dies bonded to the sites on the IHS components.
 19. The apparatus of claim 14, further comprising a substrate panel including a plurality of package substrates coupled with the perimeter ribs of the IHS panel and each of the plurality of IC dies.
 20. An electronic appliance comprising: a network controller; a system memory; and a processor, wherein the processor comprises: a package substrate; an IC die mounted to the substrate; and an IHS bonded and thermally coupled to the die such that the die is between the substrate and the IHS, the IHS being coextensive in its width and in its length with respect to the package substrate, wherein the IHS includes a perimeter rib that extends to and bonds with a top surface of the package substrate.
 21. The electronic appliance of claim 20, wherein the IHS comprises copper.
 22. The electronic appliance of claim 20, wherein the IHS comprises a porous plug.
 23. The electronic appliance of claim 20, wherein the IHS comprises an opening that extends through a thickness of the IHS.
 24. The electronic appliance of claim 20, wherein the IHS comprises a protruding gate near the IC die, the gate being coextensive in height with respect to the IC die.
 25. The electronic appliance of claim 20, wherein the IHS comprises an opening in the perimeter wall at least partially filled with an underfill material. 